Digital VLSI Design and Simulation with Verilog, , Wiley, Govind S. Patel, Sanjeet K. Sinha, Sobhit Saxena, Suman Lata Tripathi,Electronics: circuits and components,Electronics engineering, HDL; PLD; SPLD; CPLD; FPGA; FPGA architecture; CMOS design; NMOS design; PMOS design; combinational circuit design; sequential circuit design; digital VLSI; analog VLSI; hardware description language; gate level model; dataflow model; Behavioral Model; switch Level Model; User Defined Primitives; Logic Synthesis,, , United States, en-UShttps://www.wiley.comHDL; PLD; SPLD; CPLD; FPGA; FPGA architecture; CMOS design; NMOS design; PMOS design; combinational circuit design; sequential circuit design; digital VLSI; analog VLSI; hardware description language; gate level model; dataflow model; Behavioral Model; switch Level Model; User Defined Primitives; Logic Synthesis, [BLURB],[CITY],,books, ebooks, biblet, Book2look